Many factors or constraints are considered in preparing a circuit design. Examples include cost, power consumption, circuit area, and clock speed. Often, improving one characteristic of the design will have a corresponding negative impact on another characteristic of the design. Thus, during the design process various compromises are made between competing design constraints. However, once a circuit design has been successfully placed and routed, the resulting placed-and-routed design is expected to satisfy the various design factors.
In some instances, a placed-and-routed circuit may not satisfy all the design constraints. For example, one or more critical paths of the circuit may not satisfy a timing constraint. In this case, the designer may either relax the timing constraint and operate the circuit at a slower clock speed, or analyze and modify the design to bring the critical paths into compliance with the timing constraint. Current computer aided design tools used in stages from the design capture stage to making the placed-and-routed design may provide limited or no support for further improving the design to achieve a greater clock rate after the design has been placed and routed.
The present invention may address one or more of the above issues.